From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 21 Sep 2015 09:52:40 +0000 (+0200)
Subject: Do not detect fsm state registers with init attribute
X-Git-Tag: yosys-0.6~148
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b66bf8bed17473b0b972671fe3c4f4c5d147e68a;p=yosys.git

Do not detect fsm state registers with init attribute
---

diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc
index fd0ae44b9..740113e35 100644
--- a/passes/fsm/fsm_detect.cc
+++ b/passes/fsm/fsm_detect.cc
@@ -110,6 +110,8 @@ static bool check_state_users(RTLIL::SigSpec sig)
 
 static void detect_fsm(RTLIL::Wire *wire)
 {
+	if (wire->attributes.count("\\init") > 0)
+		return;
 	if (wire->attributes.count("\\fsm_encoding") > 0 || wire->width <= 1)
 		return;
 	if (sig_at_port.check_any(assign_map(RTLIL::SigSpec(wire))))