From: Florent Kermarrec Date: Sun, 9 Feb 2020 18:01:03 +0000 (+0100) Subject: soc: fix unit-tests X-Git-Tag: 24jan2021_ls180~677^2~37 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b676a559fdfb0066e264fb58af8f3a9617b214f2;p=litex.git soc: fix unit-tests --- diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 476eeda1..51d08aa3 100755 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1,5 +1,3 @@ -#!/usr/bin/env python3 - # This file is Copyright (c) 2020 Florent Kermarrec # License: BSD @@ -710,8 +708,8 @@ class SoC(Module): slaves = bus_slaves, register = True, timeout_cycles = self.bus.timeout) - if hasattr(self, "ctrl") and self.bus.timeout is not None: - self.comb += self.ctrl.bus_error.eq(self.bus_interconnect.timeout.error) + if hasattr(self, "ctrl") and self.bus.timeout is not None: + self.comb += self.ctrl.bus_error.eq(self.bus_interconnect.timeout.error) # SoC CSR Interconnect --------------------------------------------------------------------- self.submodules.csr_bankarray = csr_bus.CSRBankArray(self, diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index bf5566b2..d5feb999 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -111,6 +111,8 @@ class SoCCore(SoC): self.integrated_sram_size = integrated_sram_size self.integrated_main_ram_size = integrated_main_ram_size + self.csr_data_width = csr_data_width + self.with_wishbone = with_wishbone self.wishbone_timeout_cycles = wishbone_timeout_cycles