From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 14 Jan 2020 07:33:37 +0000 (-0800)
Subject: abc9_ops: ignore inouts of all cell outputs for topo ordering
X-Git-Tag: working-ls180~849^2~28
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b678b15c6d0d14580ca18e89f86926eabf8fead0;p=yosys.git

abc9_ops: ignore inouts of all cell outputs for topo ordering
---

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 4da10d94b..d7ebfdf3f 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -488,7 +488,9 @@ void reintegrate(RTLIL::Module *module)
 			RTLIL::SigBit a_bit = mapped_cell->getPort(ID::A);
 			RTLIL::SigBit y_bit = mapped_cell->getPort(ID::Y);
 			bit_users[a_bit].insert(mapped_cell->name);
-			bit_drivers[y_bit].insert(mapped_cell->name);
+			// Ignore inouts for topo ordering
+			if (y_bit.wire && !(y_bit.wire->port_input && y_bit.wire->port_output))
+				bit_drivers[y_bit].insert(mapped_cell->name);
 
 			if (!a_bit.wire) {
 				mapped_cell->setPort(ID::Y, module->addWire(NEW_ID));
@@ -598,7 +600,9 @@ void reintegrate(RTLIL::Module *module)
 				for (const auto &i : inputs)
 					bit_users[i].insert(mapped_cell->name);
 				for (const auto &i : outputs)
-					bit_drivers[i].insert(mapped_cell->name);
+					// Ignore inouts for topo ordering
+					if (i.wire && !(i.wire->port_input && i.wire->port_output))
+						bit_drivers[i].insert(mapped_cell->name);
 			}
 
 			int input_count = 0, output_count = 0;