From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 27 Oct 2018 04:14:28 +0000 (+0100)
Subject: redirect freg_t to sv_freg_t
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b680d87e1e0c7f7ecbb404a04e58dfbcb32071b3;p=riscv-isa-sim.git

redirect freg_t to sv_freg_t
---

diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index c5029d0..1f20354 100644
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -15,7 +15,7 @@ void (sv_proc_t::WRITE_FRD)(sv_float64_t value)
     DO_WRITE_FREG( _insn->rd(), freg(value) );
 }
 
-void (sv_proc_t::WRITE_FRD)(freg_t value)
+void (sv_proc_t::WRITE_FRD)(sv_freg_t value)
 {
     fprintf(stderr, "WRITE_FRD fsv_reg_t %lx\n", value.v[0]);
     DO_WRITE_FREG( _insn->rd(), freg(value) );
@@ -81,7 +81,7 @@ void (sv_proc_t::WRITE_RD)(sv_reg_t const& value)
 
 //#define OFFSDIV
 
-void (sv_proc_t::DO_WRITE_FREG)(reg_spec_t const& spec, freg_t const& value)
+void (sv_proc_t::DO_WRITE_FREG)(reg_spec_t const& spec, sv_freg_t const& value)
 {
     //WRITE_REG( reg, value ); // XXX TODO: replace properly
     reg_t reg = spec.reg;
@@ -125,7 +125,7 @@ void (sv_proc_t::WRITE_REG)(reg_spec_t const& spec, sv_reg_t const& value)
     STATE.XPR.write(reg, wval);
 }
 
-freg_t (sv_proc_t::READ_FREG)(reg_spec_t const& spec)
+sv_freg_t (sv_proc_t::READ_FREG)(reg_spec_t const& spec)
 {
     reg_t reg = spec.reg;
     uint8_t elwidth = _insn->reg_elwidth(reg, true);
@@ -187,28 +187,28 @@ sv_reg_t sv_proc_t::get_rvc_sp()
     return get_intreg({X_SP, _insn->get_sp_offs()});
 }
 
-freg_t sv_proc_t::get_frs1()
+sv_freg_t sv_proc_t::get_frs1()
 {
     reg_spec_t spec = _insn->rs1();
     return READ_FREG(spec);
 }
 
-freg_t sv_proc_t::get_frs3()
+sv_freg_t sv_proc_t::get_frs3()
 {
     return READ_FREG(_insn->rs3());
 }
 
-freg_t sv_proc_t::get_frs2()
+sv_freg_t sv_proc_t::get_frs2()
 {
     return READ_FREG(_insn->rs2());
 }
 
-freg_t sv_proc_t::get_rvc_frs2s()
+sv_freg_t sv_proc_t::get_rvc_frs2s()
 {
     return READ_FREG(_insn->rvc_rs2s());
 }
 
-freg_t sv_proc_t::get_rvc_frs2()
+sv_freg_t sv_proc_t::get_rvc_frs2()
 {
     return READ_FREG(_insn->rvc_rs2());
 }
@@ -502,7 +502,7 @@ sv_reg_t sv_proc_t::sv_reg_uint32(sv_reg_t const& v)
     return sv_reg_t((uint64_t)x);
 }
 
-sv_float32_t (sv_proc_t::f32)(freg_t x)
+sv_float32_t (sv_proc_t::f32)(sv_freg_t x)
 {
     return ::f32(x);
 }
@@ -512,7 +512,7 @@ sv_float32_t (sv_proc_t::f32)(sv_reg_t const& v)
     return ::f32(x);
 }
 
-sv_float64_t (sv_proc_t::f64)(freg_t v)
+sv_float64_t (sv_proc_t::f64)(sv_freg_t v)
 {
     return ::f64(v);
 }
diff --git a/riscv/sv_insn_redirect.h b/riscv/sv_insn_redirect.h
index d5ee76f..ab484bb 100644
--- a/riscv/sv_insn_redirect.h
+++ b/riscv/sv_insn_redirect.h
@@ -59,6 +59,7 @@ class insn_t;
 typedef float32_t sv_float32_t;
 typedef float64_t sv_float64_t;
 typedef float128_t sv_float128_t;
+typedef freg_t sv_freg_t;
 
 class sv_proc_t
 {
@@ -77,14 +78,14 @@ public:
     void (WRITE_RVC_RS1S)(sv_reg_t const& value); // XXX TODO investigate
     //void (WRITE_RVC_RS1S)(sv_sreg_t value); // XXX TODO investigate
     //void (WRITE_REG)(reg_t reg, uint64_t value);
-    void (DO_WRITE_FREG)(reg_spec_t const&reg, freg_t const& value);
+    void (DO_WRITE_FREG)(reg_spec_t const&reg, sv_freg_t const& value);
     void (WRITE_REG)(reg_spec_t const&reg, sv_reg_t const& value);
     //void (WRITE_REG)(reg_t reg, sv_sreg_t value);
-    void (WRITE_FRD)(freg_t value);
+    void (WRITE_FRD)(sv_freg_t value);
     void (WRITE_FRD)(sv_float64_t value);
     void (WRITE_FRD)(sv_float32_t value);
     reg_t (READ_REG)(reg_spec_t const& i);
-    freg_t (READ_FREG)(reg_spec_t const& i);
+    sv_freg_t (READ_FREG)(reg_spec_t const& i);
 
     processor_t *p;
     sv_insn_t *_insn;
@@ -122,11 +123,11 @@ public:
 
     sv_reg_t uint64_max();
 
-    freg_t get_frs1();
-    freg_t get_frs2();
-    freg_t get_frs3();
-    freg_t get_rvc_frs2();
-    freg_t get_rvc_frs2s();
+    sv_freg_t get_frs1();
+    sv_freg_t get_frs2();
+    sv_freg_t get_frs3();
+    sv_freg_t get_rvc_frs2();
+    sv_freg_t get_rvc_frs2s();
 
     sv_sreg_t (sext_xlen)(sv_sreg_t const& v); // WARNING...
     sv_sreg_t (sext_xlen)(sv_reg_t const& v); // WARNING...
@@ -166,10 +167,10 @@ public:
     sv_reg_t sv_reg_uint32(sv_reg_t const&);
     sv_reg_t sv_reg_int32(sv_reg_t const&);
 
-    sv_float64_t (f64)(freg_t  v);
+    sv_float64_t (f64)(sv_freg_t  v);
     sv_float64_t (f64)(sv_reg_t  const&v);
     sv_float32_t (f32)(sv_reg_t  const&v);
-    sv_float32_t (f32)(freg_t v);
+    sv_float32_t (f32)(sv_freg_t v);
     sv_reg_t (f32_classify)(sv_float32_t  a);
     sv_reg_t (f64_classify)(sv_float64_t  a);
     sv_reg_t (f128_classify)(sv_float128_t  a);