From: lkcl <lkcl@web>
Date: Sat, 21 Nov 2020 21:27:53 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~1701
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b685ac4d7f331bac78f1f81680deb1f3ad4c4d7d;p=libreriscv.git

---

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index e2c5ac593..7f8f25373 100644
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -6,7 +6,8 @@ Fundamental design principles:
 
 * Simplicity of introduction and implementation on the existing OpenPOWER ISA
 * Effectively a hardware for-loop, pausing PC, issuing multiple scalar operations
-* Preserving the underlying scalar execution dependencies as if the for-loop had been expanded as actual scalar instructions.
+* Preserving the underlying scalar execution dependencies as if the for-loop had been expanded as actual scalar instructions
+  (termed "preserving Program Order")
 * Augments ("tags") existing instructions, providing Vectorisation "context" rather than adding new ones.
 * Does not modify or deviate from the underly scalar OpenPOWER ISA unless it provides significant performance or other advantage to do so in the Vector space (dropping XER.SO and OE=1 for example)