From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 31 Jan 2020 14:12:18 +0000 (+0100)
Subject: soc_core: add UART bridge support (simplify having to do it externally)
X-Git-Tag: 24jan2021_ls180~698
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b69f2993e41d3fa881398a28c420a8018d38bf46;p=litex.git

soc_core: add UART bridge support (simplify having to do it externally)
---

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 33240ff2..597b2aa2 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -243,6 +243,9 @@ class SoCCore(Module):
                 self.submodules.uart = uart.UART()
                 if uart_name == "stub":
                     self.comb += self.uart.sink.ready.eq(1)
+            elif uart_name == "bridge":
+                self.submodules.uart = uart.UARTWishboneBridge(platform.request("serial"), clk_freq, uart_baudrate)
+                self.add_wb_master(self.uart.wishbone)
             elif uart_name == "crossover":
                 self.submodules.uart = uart.UARTCrossover()
             else: