From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 24 Dec 2014 15:26:18 +0000 (+0100)
Subject: Fixed off-by-one bug in "hierarchy -check" for positional module args
X-Git-Tag: yosys-0.5~227
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b6a7e21d2ee773b2eedf55ded913b034e916fa27;p=yosys.git

Fixed off-by-one bug in "hierarchy -check" for positional module args
---

diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 028a0f0c2..e95947a92 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -206,9 +206,9 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
 			for (auto &conn : cell->connections())
 				if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') {
 					int id = atoi(conn.first.c_str()+1);
-					if (id < 0 || id >= GetSize(mod->ports))
+					if (id <= 0 || id > GetSize(mod->ports))
 						log_error("Module `%s' referenced in module `%s' in cell `%s' has only %d ports, requested port %d.\n",
-								log_id(cell->type), log_id(module), log_id(cell), GetSize(mod->ports), id + 1);
+								log_id(cell->type), log_id(module), log_id(cell), GetSize(mod->ports), id);
 				} else if (mod->wire(conn.first) == nullptr || mod->wire(conn.first)->port_id == 0)
 					log_error("Module `%s' referenced in module `%s' in cell `%s' does not have a port named '%s'.\n",
 							log_id(cell->type), log_id(module), log_id(cell), log_id(conn.first));