From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 4 Sep 2020 12:01:09 +0000 (+0100)
Subject: add means to run hello_world.bin under simulation
X-Git-Tag: semi_working_ecp5~205
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b6a9b9057d6694df7f1d20d8ad073ff49e0e1355;p=soc.git

add means to run hello_world.bin under simulation
works with both microwatt and libresoc
---

diff --git a/src/soc/litex/florent/sim.py b/src/soc/litex/florent/sim.py
index 23d0c6c0..02d5e690 100755
--- a/src/soc/litex/florent/sim.py
+++ b/src/soc/litex/florent/sim.py
@@ -51,7 +51,9 @@ class LibreSoCSim(SoCSDRAM):
         ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
                     "tests/3.bin"
         #ram_fname = "/tmp/test.bin"
-        ram_fname = None
+        #ram_fname = None
+        ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
+                    "hello_world/hello_world.bin"
 
         ram_init = []
         if ram_fname:
@@ -66,6 +68,9 @@ class LibreSoCSim(SoCSDRAM):
             # without sram nothing works, therefore move it to higher up
             self.mem_map["sram"] = 0x90000000
 
+            # put UART at 0xc000200 (w00t!  this works!)
+            self.csr_map["uart"] = 4
+
 
         # SoCCore -------------------------------------------------------------
         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,