From: Luke Kenneth Casson Leighton Date: Fri, 9 Apr 2021 00:09:32 +0000 (+0100) Subject: test firmware upload program needed to branch back further in order to loop X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b6ad5ab2950a520b35810bf6cf47426185284b93;p=soc.git test firmware upload program needed to branch back further in order to loop --- diff --git a/src/soc/debug/firmware_upload.py b/src/soc/debug/firmware_upload.py index 7480e8d4..9fdef8b7 100644 --- a/src/soc/debug/firmware_upload.py +++ b/src/soc/debug/firmware_upload.py @@ -163,7 +163,7 @@ if __name__ == '__main__': lst = ["addi 9, 0, 0x10", # i = 16 "addi 9,9,-1", # i = i - 1 "cmpi 2,1,9,12", # compare 9 to value 12, store in CR2 - "bc 4,10,-8", # branch if CR2 "test was != 12" + "bc 4,10,-16", # branch if CR2 "test was != 12" 'attn', ] diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index 92f85784..dfd0b96a 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -908,8 +908,6 @@ class TestIssuerInternal(Elaboratable): # address of the next instruction, in the absence of a branch # depends on the instruction size nia = Signal(64) - with m.If(core_rst): - sync += nia.eq(0) # connect up debug signals # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o) @@ -980,6 +978,10 @@ class TestIssuerInternal(Elaboratable): exec_insn_valid_i, exec_insn_ready_o, exec_pc_valid_o, exec_pc_ready_i) + # whatever was done above, over-ride it if core reset is held + with m.If(core_rst): + sync += nia.eq(0) + # this bit doesn't have to be in the FSM: connect up to read # regfiles on demand from DMI self.do_dmi(m, dbg)