From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 9 May 2020 14:06:02 +0000 (+0100)
Subject: comment where ALUIntermediateData to go
X-Git-Tag: div_pipeline~1316
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b6aee5d13d5919381c40e886b0a2a00a4e5d5c4f;p=soc.git

comment where ALUIntermediateData to go
---

diff --git a/src/soc/alu/main_stage.py b/src/soc/alu/main_stage.py
index 07fb0180..7d79b1a1 100644
--- a/src/soc/alu/main_stage.py
+++ b/src/soc/alu/main_stage.py
@@ -18,7 +18,7 @@ class ALUMainStage(PipeModBase):
         return ALUInputData(self.pspec)
 
     def ospec(self):
-        return ALUOutputData(self.pspec)
+        return ALUOutputData(self.pspec) # TODO: ALUIntermediateData
 
     def elaborate(self, platform):
         m = Module()
diff --git a/src/soc/alu/output_stage.py b/src/soc/alu/output_stage.py
index 1a8a82b6..188ea4ab 100644
--- a/src/soc/alu/output_stage.py
+++ b/src/soc/alu/output_stage.py
@@ -13,7 +13,7 @@ class ALUOutputStage(PipeModBase):
         super().__init__(pspec, "output")
 
     def ispec(self):
-        return ALUOutputData(self.pspec)
+        return ALUOutputData(self.pspec) # TODO: ALUIntermediateData
 
     def ospec(self):
         return ALUOutputData(self.pspec)