From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 11 Jul 2020 21:53:19 +0000 (+0100)
Subject: add endian
X-Git-Tag: div_pipeline~88
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b6b082636e16da171372b370df6b52bb19e639de;p=soc.git

add endian
---

diff --git a/src/soc/fu/compunits/test/test_ldst_compunit.py b/src/soc/fu/compunits/test/test_ldst_compunit.py
index 7cbf6d90..65a6be70 100644
--- a/src/soc/fu/compunits/test/test_ldst_compunit.py
+++ b/src/soc/fu/compunits/test/test_ldst_compunit.py
@@ -6,12 +6,13 @@ from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase, get_cu_inputs
 from soc.fu.compunits.compunits import LDSTFunctionUnit
 from soc.fu.compunits.test.test_compunit import TestRunner
 from soc.fu.test.common import ALUHelpers
+from soc.config.endian import bigendian
 
 
 class LDSTTestRunner(TestRunner):
     def __init__(self, test_data):
         super().__init__(test_data, LDSTFunctionUnit, self,
-                         Function.LDST)
+                         Function.LDST, bigendian)
 
     def get_cu_inputs(self, dec2, sim):
         """naming (res) must conform to LDSTFunctionUnit input regspec