From: lkcl <lkcl@web>
Date: Thu, 23 Jun 2022 11:30:35 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1581
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b6c8d517a106e183474adf6bc110bcb3a63c22a9;p=libreriscv.git

---

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index 8546f6dca..7c4330113 100644
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -4,16 +4,19 @@ Obligatory Dilbert:
 
 <img src="https://assets.amuniversal.com/7fada35026ca01393d3d005056a9545d" width="600" />
 
-===
+Links:
 
-# DRAFT SV (Simple Scalar Vectorisation) for the Power ISA
+* <https://bugs.libre-soc.org/show_bug.cgi?id=213>
+* <https://youtu.be/ZQ5hw9AwO1U> walkthrough video (19jun2022)
 
 **SV is in DRAFT STATUS**. SV has not yet been submitted to the OpenPOWER Foundation ISA WG for review.
 
-* <https://bugs.libre-soc.org/show_bug.cgi?id=213>
-* <https://youtu.be/ZQ5hw9AwO1U> walkthrough video (19jun2022)
+===
+
+# DRAFT SV (Simple Scalar Vectorisation) for the Power ISA
 
-SV is designed as a Scalable Vector ISA for Hybrid 3D CPU GPU VPU workloads.
+SV is designed as a strict RISC-paradigm
+Scalable Vector ISA for Hybrid 3D CPU GPU VPU workloads.
 As such it brings features normally only found in Cray Supercomputers
 (Cray-1, NEC SX-Aurora)
 and in GPUs, but keeps strictly to a *Simple* RISC principle of leveraging
@@ -33,7 +36,10 @@ Fundamental design principles:
   (termed "preserving Program Order")
 * Augments ("tags") existing instructions, providing Vectorisation
   "context" rather than adding new instructions.
-* Does not modify or deviate from the underlying scalar Power ISA
+* Strictly does not interfere with or alter the non-Scalable Power ISA
+  in any way
+* In the Prefix space, does not modify or deviate from the underlying
+  scalar Power ISA
   unless it provides significant performance or other advantage to do so
   in the Vector space (dropping the "sticky" characteristics
   of XER.SO and CR0.SO for example)
@@ -41,6 +47,8 @@ Fundamental design principles:
   dependency hazards, allowing standard
   high performance superscalar multi-issue
   micro-architectures to be leveraged.
+* Divided into Compliancy Levels to reduce cost of implementation for
+  specific needs.
 
 Advantages of these design principles: