From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Tue, 9 Jun 2020 14:50:18 +0000 (+0200)
Subject: Fix nMigen migration bug, and rename from LiteDRAM to gram
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b6c975cdf2eb9f551bc89133d8dcbaa566c4c06b;hp=c933f29f4068e9a67a918c72ecbbc9ba0f41b155;p=gram.git

Fix nMigen migration bug, and rename from LiteDRAM to gram
---

diff --git a/gram/frontend/adaptation.py b/gram/frontend/adaptation.py
index 529bf65..80c4d9a 100644
--- a/gram/frontend/adaptation.py
+++ b/gram/frontend/adaptation.py
@@ -107,7 +107,7 @@ class gramNativePortDownConverter(Elaboratable):
         ratio = port_from.data_width//port_to.data_width
         mode = port_from.mode
 
-        counter = Signal(max=ratio)
+        counter = Signal(range(ratio))
         counter_reset = Signal()
         counter_ce = Signal()
 
@@ -345,7 +345,7 @@ class gramNativeReadPortUpConverter(Elaboratable):
 # LiteDRAMNativePortConverter ----------------------------------------------------------------------
 
 
-class LiteDRAMNativePortConverter(Elaboratable):
+class gramNativePortConverter(Elaboratable):
     def __init__(self, port_from, port_to, reverse=False):
         assert port_from.clock_domain == port_to.clock_domain
         assert port_from.mode == port_to.mode