From: lkcl <lkcl@web>
Date: Wed, 23 Jun 2021 09:48:59 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~734
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b6d7c254dad5c754cada05f9580343141abe64e3;p=libreriscv.git

---

diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn
index e00d3678e..35d34698e 100644
--- a/openpower/sv/overview.mdwn
+++ b/openpower/sv/overview.mdwn
@@ -71,7 +71,7 @@ registers from 32 to 64 bit).
 
 ## SV
 
-The fundamentals are:
+The fundamentals are (just like x86 "REP"):
 
 * The Program Counter (PC) gains a "Sub Counter" context (Sub-PC)
 * Vectorisation pauses the PC and runs a Sub-PC loop from 0 to VL-1