From: lkcl <lkcl@web>
Date: Sat, 15 Apr 2023 22:44:42 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls009_v1~57
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b6e0cd07385f3bf0a1689884e4a9b1d05117485c;p=libreriscv.git

---

diff --git a/openpower/sv/remap.mdwn b/openpower/sv/remap.mdwn
index 5bf81df42..4d50fc14e 100644
--- a/openpower/sv/remap.mdwn
+++ b/openpower/sv/remap.mdwn
@@ -40,7 +40,8 @@ literally any instruction: CRs, Arithmetic, Logical, LD/ST, anything.
 
 When SUBVL is greater than 1 a given group of Subvector
 elements are kept together: effectively the group becomes the
-element, and the group is REMAPed together.
+element, and with REMAP applying to elements
+(not sub-elements) each group is REMAPed together.
 Swizzle *can* however be applied to the same
 instruction as REMAP, providing re-sequencing of
 Subvector elements which REMAP cannot. Also as explained in [[sv/mv.swizzle]], [[sv/mv.vec]] and the [[svp64/appendix]], Pack and Unpack Mode bits