From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 25 Oct 2018 06:28:49 +0000 (+0100)
Subject: make reg_spec_t offset a pointer, sometimes it needs to be NULL
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b6e4f3e51fc5e395656f9cdf24a7bb4cac5e7985;p=riscv-isa-sim.git

make reg_spec_t offset a pointer, sometimes it needs to be NULL
---

diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc
index f8b5522..5de338f 100644
--- a/riscv/insn_template_sv.cc
+++ b/riscv/insn_template_sv.cc
@@ -77,7 +77,7 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
   reg_t _target_reg = 0;
   reg_t *target_reg = NULL;
 #endif
-  reg_spec_t sp = {0,0};
+  reg_spec_t sp = {0, insn.get_sp_offs()};
   if (vlen > 0)
   {
     fprintf(stderr, "pre-ex reg %s %x %ld rd %ld rs1 %ld rs2 %ld vlen %d\n",
diff --git a/riscv/sv.cc b/riscv/sv.cc
index 7c2f0a1..8bf1554 100644
--- a/riscv/sv.cc
+++ b/riscv/sv.cc
@@ -130,11 +130,9 @@ bool sv_insn_t::sv_check_reg(bool intreg, uint64_t reg)
  * of SV.  it's "supposed" to "just" be a vectorisation API. it isn't:
  * it's quite a bit more.
  */
-reg_spec_t sv_insn_t::remap(uint64_t reg, bool intreg, int voffs)
+reg_spec_t sv_insn_t::remap(uint64_t reg, bool intreg, int *voffs)
 {
-  reg_spec_t spec;
-  spec.reg = reg;
-  spec.offset = voffs;
+  reg_spec_t spec = {reg, voffs};
   // okaay so first determine which map to use.  intreg is passed
   // in (ultimately) from id_regs.py's examination of the use of
   // FRS1/RS1, WRITE_FRD/WRITE_RD, which in turn gets passed
@@ -166,7 +164,7 @@ reg_spec_t sv_insn_t::remap(uint64_t reg, bool intreg, int voffs)
   // aaand now, as it's a "vector", FINALLY we can add on the loop-offset
   // which was passed in to the sv_insn_t constructor (by reference)
   // and, at last, we have "parallelism" a la contiguous registers.
-  reg += voffs; // wheww :)
+  reg += *voffs; // wheww :)
 
   spec.reg = reg;
   return spec;
@@ -222,7 +220,6 @@ reg_t sv_insn_t::predicate(uint64_t reg, bool intreg, bool &zeroing)
 reg_spec_t sv_insn_t::predicated(reg_spec_t const& spec, int offs, uint64_t pred)
 {
     reg_spec_t res = spec;
-    res.offset = offs;
     if (pred & (1<<offs))
     {
         return res;
diff --git a/riscv/sv_decode.h b/riscv/sv_decode.h
index e22b6aa..e0a058e 100644
--- a/riscv/sv_decode.h
+++ b/riscv/sv_decode.h
@@ -29,7 +29,7 @@ class processor_t;
 struct reg_spec_t
 {
     reg_t reg;
-    int offset;
+    int *offset;
 };
 
 class sv_insn_t: public insn_t
@@ -110,13 +110,15 @@ public:
     {
         vloop_continue = true;
     }
-    return remap(reg, isint, *offs);
+    return remap(reg, isint, offs);
   }
 
   uint64_t get_saved_branch_addr() { return save_branch_addr; }
   uint64_t get_saved_branch_rd() { return save_branch_rd; }
   uint64_t get_if_one_reg_vectorised() { return at_least_one_reg_vectorised; }
 
+  int *get_sp_offs() { return offs_sp; }
+
 private:
   bool vloop_continue;
   bool at_least_one_reg_vectorised;
@@ -138,7 +140,7 @@ private:
 
   // remaps the register through the lookup table.
   // will need to take the current loop index/offset somehow
-  reg_spec_t remap(uint64_t reg, bool isint, int offs);
+  reg_spec_t remap(uint64_t reg, bool isint, int *offs);
 
   reg_spec_t predicated(reg_spec_t const& reg, int offs, uint64_t pred);
 };
diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index 46b4d7b..da1732b 100644
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -135,7 +135,7 @@ GET_REG(rvc_rs2)
 
 sv_reg_t sv_proc_t::get_rvc_sp()
 {
-    return get_intreg({X_SP, 0}); //_insn->rvc_sp()); // XXX TODO: work out redirection
+    return get_intreg({X_SP, _insn->get_sp_offs()});
 }
 
 freg_t sv_proc_t::get_frs1()