From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 4 Jun 2019 03:21:41 +0000 (-0700)
Subject: Typo
X-Git-Tag: working-ls180~1208^2~211
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b6e59741ae6e4ec57affb9ab168a9d08cdb6d04f;p=yosys.git

Typo
---

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index c8450f8d1..16b8b4949 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -262,7 +262,7 @@ module FDCE ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input
 endmodule
 
 (* abc_box_id = 9, abc_flop /*, lib_whitebox*/ *)
-module FDPE ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_q *) input D, input PRE);
+module FDPE ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input D, input PRE);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;