From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 3 Sep 2013 22:06:53 +0000 (+0200)
Subject: actorlib/spi: add optional irq generation on DMAController
X-Git-Tag: 24jan2021_ls180~2099^2~464
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b6eb97e49fa44b5e189dba3a2888c8e4bbe34e51;p=litex.git

actorlib/spi: add optional irq generation on DMAController
---

diff --git a/migen/actorlib/spi.py b/migen/actorlib/spi.py
index 81353005..10f9190b 100644
--- a/migen/actorlib/spi.py
+++ b/migen/actorlib/spi.py
@@ -6,6 +6,7 @@ from migen.flow.actor import *
 from migen.flow.network import *
 from migen.flow import plumbing
 from migen.actorlib import misc
+from migen.bank.eventmanager import *
 
 # layout is a list of tuples, either:
 # - (name, nbits, [reset value], [alignment bits])
@@ -109,7 +110,7 @@ class Collector(Module, AutoCSR):
 		]
 
 class _DMAController(Module):
-	def __init__(self, bus_accessor, bus_aw, bus_dw, mode, base_reset=0, length_reset=0):
+	def __init__(self, bus_accessor, bus_aw, bus_dw, mode, base_reset=0, length_reset=0, generate_irq=False):
 		self.alignment_bits = bits_for(bus_dw//8) - 1
 		layout = [
 			("length", bus_aw + self.alignment_bits, length_reset, self.alignment_bits),
@@ -123,8 +124,23 @@ class _DMAController(Module):
 		if hasattr(self.generator, "trigger"):
 			self.trigger = self.generator.trigger
 
+		self.generate_irq = generate_irq
+		if generate_irq:
+			self.submodules.ev = EventManager()
+			self.ev.done = EventSourcePulse()
+			self.ev.finalize()
+
+			r_busy_d = Signal()
+
+			self.sync += r_busy_d.eq(self.r_busy.status)
+			self.comb += self.ev.done.trigger.eq(~self.r_busy.status & r_busy_d)
+
+
 	def get_csrs(self):
-		return self.generator.get_csrs() + [self.r_busy]
+		csrs = self.generator.get_csrs() + [self.r_busy]
+		if self.generate_irq:
+			csrs += self.ev.get_csrs()
+		return csrs
 
 class DMAReadController(_DMAController):
 	def __init__(self, bus_accessor, *args, **kwargs):