From: H.J. Lu <hjl@gcc.gnu.org>
Date: Wed, 8 Jul 2015 16:19:06 +0000 (-0700)
Subject: Don't pass/return vectors in registers for IAMCU
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b6f485e7af0777a6ee40fc0bd662b02022b28d71;p=gcc.git

Don't pass/return vectors in registers for IAMCU

Vectors should be passed in memory for IAMCU.  No warning for vector ABI
change for IAMCU since IAMCU ABI won't change.

gcc/

	PR target/66806
	* config/i386/i386.c (type_natural_mode): Don't warn vector ABI
	change for IAMCU.
	(function_arg_advance_32): Don't pass vectors in registers for
	IAMCU.
	(function_arg_32): Likewise.
	(ix86_return_in_memory): Don't return vectors in registers for
	IAMCU.

gcc/testsuite/

	PR target/66806
	* gcc.target/i386/pr66806.c: New test.

From-SVN: r225564
---

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 112eb1c6ef7..55a32acc581 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -6685,7 +6685,7 @@ type_natural_mode (const_tree type, const CUMULATIVE_ARGS *cum,
 	    if (GET_MODE_NUNITS (mode) == TYPE_VECTOR_SUBPARTS (type)
 		&& GET_MODE_INNER (mode) == innermode)
 	      {
-		if (size == 64 && !TARGET_AVX512F)
+		if (size == 64 && !TARGET_AVX512F && !TARGET_IAMCU)
 		  {
 		    static bool warnedavx512f;
 		    static bool warnedavx512f_ret;
@@ -6705,7 +6705,7 @@ type_natural_mode (const_tree type, const CUMULATIVE_ARGS *cum,
 
 		    return TYPE_MODE (type);
 		  }
-		else if (size == 32 && !TARGET_AVX)
+		else if (size == 32 && !TARGET_AVX && !TARGET_IAMCU)
 		  {
 		    static bool warnedavx;
 		    static bool warnedavx_ret;
@@ -6726,7 +6726,8 @@ type_natural_mode (const_tree type, const CUMULATIVE_ARGS *cum,
 		    return TYPE_MODE (type);
 		  }
 		else if (((size == 8 && TARGET_64BIT) || size == 16)
-			 && !TARGET_SSE)
+			 && !TARGET_SSE
+			 && !TARGET_IAMCU)
 		  {
 		    static bool warnedsse;
 		    static bool warnedsse_ret;
@@ -6744,7 +6745,9 @@ type_natural_mode (const_tree type, const CUMULATIVE_ARGS *cum,
 			  warnedsse_ret = true;
 		      }
 		  }
-		else if ((size == 8 && !TARGET_64BIT) && !TARGET_MMX)
+		else if ((size == 8 && !TARGET_64BIT)
+			 && !TARGET_MMX
+			 && !TARGET_IAMCU)
 		  {
 		    static bool warnedmmx;
 		    static bool warnedmmx_ret;
@@ -7552,7 +7555,7 @@ function_arg_advance_32 (CUMULATIVE_ARGS *cum, machine_mode mode,
     {
       /* Intel MCU psABI passes scalars and aggregates no larger than 8
 	 bytes in registers.  */
-      if (bytes <= 8)
+      if (!VECTOR_MODE_P (mode) && bytes <= 8)
 	goto pass_in_reg;
       return res;
     }
@@ -7809,7 +7812,7 @@ function_arg_32 (CUMULATIVE_ARGS *cum, machine_mode mode,
     {
       /* Intel MCU psABI passes scalars and aggregates no larger than 8
 	 bytes in registers.  */
-      if (bytes <= 8)
+      if (!VECTOR_MODE_P (mode) && bytes <= 8)
 	goto pass_in_reg;
       return NULL_RTX;
     }
@@ -8679,7 +8682,7 @@ ix86_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
       /* Intel MCU psABI returns scalars and aggregates no larger than 8
 	 bytes in registers.  */
       if (TARGET_IAMCU)
-	return size > 8;
+	return VECTOR_MODE_P (mode) || size > 8;
 
       if (mode == BLKmode)
 	return true;
diff --git a/gcc/testsuite/gcc.target/i386/pr66806.c b/gcc/testsuite/gcc.target/i386/pr66806.c
new file mode 100644
index 00000000000..2486c5b5e71
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr66806.c
@@ -0,0 +1,65 @@
+/* { dg-do compile { target ia32 } } */
+/* { dg-options "-mno-sse -mno-mmx -miamcu" } */
+
+/* AVX512F and AVX512BW modes.  */
+typedef unsigned char V64QImode __attribute__((vector_size(64)));
+typedef unsigned short V32HImode __attribute__((vector_size(64)));
+typedef unsigned int V16SImode __attribute__((vector_size(64)));
+typedef unsigned long long V8DImode __attribute__((vector_size(64)));
+typedef float V16SFmode __attribute__((vector_size(64)));
+typedef double V8DFmode __attribute__((vector_size(64)));
+
+/* AVX and AVX2 modes.  */
+typedef unsigned char V32QImode __attribute__((vector_size(32)));
+typedef unsigned short V16HImode __attribute__((vector_size(32)));
+typedef unsigned int V8SImode __attribute__((vector_size(32)));
+typedef unsigned long long V4DImode __attribute__((vector_size(32)));
+typedef float V8SFmode __attribute__((vector_size(32)));
+typedef double V4DFmode __attribute__((vector_size(32)));
+
+/* SSE1 and SSE2 modes.  */
+typedef unsigned char V16QImode __attribute__((vector_size(16)));
+typedef unsigned short V8HImode __attribute__((vector_size(16)));
+typedef unsigned int V4SImode __attribute__((vector_size(16)));
+typedef unsigned long long V2DImode __attribute__((vector_size(16)));
+typedef float V4SFmode __attribute__((vector_size(16)));
+typedef double V2DFmode __attribute__((vector_size(16)));
+
+/* MMX and 3DNOW modes.  */
+typedef unsigned char V8QImode __attribute__((vector_size(8)));
+typedef unsigned short V4HImode __attribute__((vector_size(8)));
+typedef unsigned int V2SImode __attribute__((vector_size(8)));
+typedef float V2SFmode __attribute__((vector_size(8)));
+
+/* Test argument loading and unloading of each.  */
+#define TEST(TYPE)					\
+extern TYPE data_##TYPE;				\
+void p_##TYPE (TYPE x) { data_##TYPE = x; }		\
+TYPE r_##TYPE (TYPE x) { return x; }			\
+void s_##TYPE (void) { p_##TYPE (data_##TYPE); }
+
+TEST(V64QImode)
+TEST(V32HImode)
+TEST(V16SImode)
+TEST(V8DImode)
+TEST(V16SFmode)
+TEST(V8DFmode)
+
+TEST(V32QImode)
+TEST(V16HImode)
+TEST(V8SImode)
+TEST(V4DImode)
+TEST(V8SFmode)
+TEST(V4DFmode)
+
+TEST(V16QImode)
+TEST(V8HImode)
+TEST(V4SImode)
+TEST(V2DImode)
+TEST(V4SFmode)
+TEST(V2DFmode)
+
+TEST(V8QImode)
+TEST(V4HImode)
+TEST(V2SImode)
+TEST(V2SFmode)