From: whitequark Date: Fri, 14 Dec 2018 16:39:52 +0000 (+0000) Subject: compat.sim: match clock period. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b6f5bfd12bbaa624a93524f20ee62f7dc8621129;p=nmigen.git compat.sim: match clock period. --- diff --git a/nmigen/compat/sim/__init__.py b/nmigen/compat/sim/__init__.py index c2a7c7b..4ee0454 100644 --- a/nmigen/compat/sim/__init__.py +++ b/nmigen/compat/sim/__init__.py @@ -18,7 +18,7 @@ def run_simulation(fragment_or_module, generators, clocks={"sync": 10}, vcd_name with Simulator(fragment, vcd_file=open(vcd_name, "w") if vcd_name else None) as sim: for domain, period in clocks.items(): - sim.add_clock(period, domain) + sim.add_clock(period / 1e9, domain) for domain, process in generators.items(): sim.add_sync_process(process, domain) sim.run()