From: lkcl <lkcl@web>
Date: Mon, 28 Mar 2022 12:50:01 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2966
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b6f7d3f22e61741c77173614b429db557e68e5f7;p=libreriscv.git

---

diff --git a/docs/pinmux.mdwn b/docs/pinmux.mdwn
index 7b7ab4b05..b62be5ca5 100644
--- a/docs/pinmux.mdwn
+++ b/docs/pinmux.mdwn
@@ -18,6 +18,11 @@ out-enable) to be routed right the way from the ASIC, all
 the way to the IO PAD, where only then does a wire bond connect
 it to a single external pin.
 
+Below, therefore is a (simplified) diagram of what is
+usually contained in an FPGA's bi-directional IO Pad,
+and consequently this is what you must also provide, and explicitly
+wire up in your ASIC's HDL.
+
 [[!img asic_iopad_gen.svg]]
 
 Designing an ASIC, there is no guarantee that the IO pad is