From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 5 Apr 2020 20:51:16 +0000 (+0100)
Subject: put regs through to ISACaller
X-Git-Tag: div_pipeline~1456
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b6fd6ec34ccea3928f96a7c193f9d041cc374efd;p=soc.git

put regs through to ISACaller
---

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 5b6e158e..2199d731 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -135,7 +135,9 @@ class ISACaller:
             self.namespace[name] = SelectableInt(val, bits=signal.width)
 
     def call(self, name):
-        function, read_regs, uninit_regs, write_regs, op_fields, form \
+        # TODO, asmregs is from the spec, e.g. add RT,RA,RB
+        # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
+        fn, read_regs, uninit_regs, write_regs, op_fields, asmregs, form \
             = self.instrs[name]
         yield from self.prep_namespace(form, op_fields)
 
@@ -150,7 +152,7 @@ class ISACaller:
             print('reading reg %d' % regnum)
             inputs.append(self.gpr(regnum))
         print(inputs)
-        results = function(self, *inputs)
+        results = fn(self, *inputs)
         print(results)
 
         if write_regs:
diff --git a/src/soc/decoder/pseudo/pywriter.py b/src/soc/decoder/pseudo/pywriter.py
index 2afc2d3c..a8f9bdab 100644
--- a/src/soc/decoder/pseudo/pywriter.py
+++ b/src/soc/decoder/pseudo/pywriter.py
@@ -26,6 +26,11 @@ class %s:
 
 """
 
+iinfo_template = """(%s, %s,
+                %s, %s,
+                %s, '%s',
+                %s)"""
+
 class PyISAWriter(ISA):
     def __init__(self):
         ISA.__init__(self)
@@ -66,11 +71,9 @@ class PyISAWriter(ISA):
                     f.write("\n")
                 # accumulate the instruction info
                 ops = repr(rused['op_fields'])
-                iinfo = """(%s, %s,
-                %s, %s,
-                %s, '%s')""" % (op_fname, rused['read_regs'],
+                iinfo = iinfo_template % (op_fname, rused['read_regs'],
                                 rused['uninit_regs'], rused['write_regs'],
-                                ops, d.form)
+                                ops, d.form, d.regs)
                 iinf += "    %s_instrs['%s'] = %s\n" % (pagename, page, iinfo)
             # write out initialisation of info, for ISACaller to use
             f.write("    %s_instrs = {}\n" % pagename)