From: Dmitry Selyutin <dmitry.selyutin@3mdeb.com>
Date: Mon, 31 Jan 2022 19:05:17 +0000 (+0000)
Subject: sv_binutils: consider RC
X-Git-Tag: sv_maxu_works-initial~525
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b701274a5f4c0c5c3fd856670c155a549c32f095;p=openpower-isa.git

sv_binutils: consider RC
---

diff --git a/src/openpower/sv/sv_binutils.py b/src/openpower/sv/sv_binutils.py
index 7fec5fdd..a6a9bb1e 100644
--- a/src/openpower/sv/sv_binutils.py
+++ b/src/openpower/sv/sv_binutils.py
@@ -13,6 +13,7 @@ from openpower.decoder.power_enums import (
     SVPtype as _SVPtype,
     SVEtype as _SVEtype,
     SVEXTRA as _SVEXTRA,
+    RC as _RC,
 )
 from openpower.decoder.power_svp64 import SVP64RM as _SVP64RM
 
@@ -375,6 +376,9 @@ def parse(path, opcode_cls):
         names = record.pop("comment").split("=")[-1].split("/")
         names = set(filter(name_filter, names))
         if names:
+            rc = _RC[record["rc"] if record["rc"] else "NONE"]
+            if rc is _RC.RC:
+                names.update({f"{name}." for name in names})
             record = dict(filter(item_filter, map(item_mapper, record.items())))
             for name in map(Name, names):
                 yield Entry(name=name, record=Record(**record))