From: Joel Stanley <joel@jms.id.au>
Date: Mon, 21 Feb 2022 13:56:25 +0000 (-0600)
Subject: yosys: Use read_verilog
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b70a6177f68880cc3724c444d3771d24d7be36ef;p=microwatt.git

yosys: Use read_verilog

Yosys changed it's command line behaviour following the v0.13 release.
Work around this by using read_verilog, which maintains the old
behaviour.

This should work fine for current yosys and be compatible with
future releases.

See https://github.com/YosysHQ/yosys/issues/3109

Signed-off-by: Joel Stanley <joel@jms.id.au>
---

diff --git a/Makefile b/Makefile
index 2d34627..e2783a2 100644
--- a/Makefile
+++ b/Makefile
@@ -192,7 +192,7 @@ fpga_files = fpga/soc_reset.vhdl \
 synth_files = $(core_files) $(soc_files) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
 
 microwatt.json: $(synth_files) $(RAM_INIT_FILE)
-	$(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; synth_ecp5 -json $@  $(SYNTH_ECP5_FLAGS)" $(uart_files)
+	$(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; read_verilog $(uart_files) $(soc_extra_v); synth_ecp5 -json $@  $(SYNTH_ECP5_FLAGS)" $(uart_files)
 
 microwatt.v: $(synth_files) $(RAM_INIT_FILE)
 	$(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; write_verilog $@"