From: lkcl <lkcl@web>
Date: Tue, 10 May 2022 09:19:31 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2277
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b77859ebdabad209e46f8017eb7e833649171c99;p=libreriscv.git

---

diff --git a/conferences/ics2022.mdwn b/conferences/ics2022.mdwn
index 9793a3409..a84684bb3 100644
--- a/conferences/ics2022.mdwn
+++ b/conferences/ics2022.mdwn
@@ -25,9 +25,11 @@ and conditional Graph walking, making full use of OpenCAPI's potential.
 Snitch also led the way, bringing back Auto-increment Load/Store from
 the CISC era, but hidden behind Tagged Registers connected to
 Coherent FIFOs leading indirectly to main Memory.  Where both Snitch
-and Extra-V used limited variants of Deterministic Loops as proof-of-concept
-of the overall , ZOLC is
-a much more extensive and well-defined
+and Extra-V used limited variants of Deterministic Loops as
+proof-of-concept to support their overall research, with only rudimentary
+processing capability,
+ZOLC is a much more deeply extensive and well-defined Deterministic Loop
+Control system that can fit directly on top of a standard ISA.
 
 SVP64 takes the Zero-Overhead Loop concept firmly into Supercomputing
 Vector Processing territory, currently limited to the register file.