From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 22 Apr 2019 18:22:29 +0000 (-0700)
Subject: Allow POs to be PIs in XAIG
X-Git-Tag: working-ls180~1237^2~167
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b780c0a7de3b0f095099461af1434624d2af0c32;p=yosys.git

Allow POs to be PIs in XAIG
---

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index e93fd35f7..a881b1b88 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -161,12 +161,8 @@ struct XAigerWriter
 			}
 		}
 
-		for (auto bit : input_bits) {
-			if (!bit.wire->port_output)
-				undriven_bits.erase(bit);
-			// Erase POs that are also PIs
-			output_bits.erase(bit);
-		}
+		for (auto bit : input_bits)
+			undriven_bits.erase(bit);
 
 		for (auto bit : output_bits)
 			if (!bit.wire->port_input)
@@ -275,7 +271,8 @@ struct XAigerWriter
 						}
 					}
 				}
-				if (!abc_box_seen) abc_box_seen = inst_module->attributes.count("\\abc_box_id");
+				if (!abc_box_seen)
+					abc_box_seen = inst_module->attributes.count("\\abc_box_id");
 
 				ff_bits.emplace_back(d, q);
 				undriven_bits.erase(q);