From: Jim Wilson <jimw@sifive.com>
Date: Sat, 8 Feb 2020 21:57:36 +0000 (-0800)
Subject: RISC-V: Improve caller-save code generation.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b780f68e025b2cf5631183e199ebf672ea463af6;p=gcc.git

RISC-V: Improve caller-save code generation.

Avoid paradoxical subregs when caller save.  This reduces stack frame size
due to smaller loads and stores, and more frequent rematerialization.

	PR target/93532
	* config/riscv/riscv.h (HARD_REGNO_CALLER_SAVE_MODE): Define.
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index ed3aac49f1b..0ae8c5442a0 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2020-02-08  Jim Wilson  <jimw@sifive.com>
+
+	PR target/93532
+	* config/riscv/riscv.h (HARD_REGNO_CALLER_SAVE_MODE): Define.
+
 2020-02-08  Uroš Bizjak  <ubizjak@gmail.com>
 	    Jakub Jelinek  <jakub@redhat.com>
 
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 19438e28fe8..567c23380fe 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -268,6 +268,13 @@ along with GCC; see the file COPYING3.  If not see
   1, 1									\
 }
 
+/* Select a register mode required for caller save of hard regno REGNO.
+   Contrary to what is documented, the default is not the smallest suitable
+   mode but the largest suitable mode for the given (REGNO, NREGS) pair and
+   it quickly creates paradoxical subregs that can be problematic.  */
+#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
+  ((MODE) == VOIDmode ? choose_hard_reg_mode (REGNO, NREGS, NULL) : (MODE))
+
 /* Internal macros to classify an ISA register's type.  */
 
 #define GP_REG_FIRST 0