From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Tue, 22 Oct 2013 13:22:40 +0000 (+0200)
Subject: Revert "genlib/fifo: support RecordP"
X-Git-Tag: 24jan2021_ls180~2099^2~458
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b782db14fcc9e4e7d825cc178e70410209183c1a;p=litex.git

Revert "genlib/fifo: support RecordP"

This reverts commit c0d2b5a78947814eeb9476fe7ca4c1e3d27e02f4.
---

diff --git a/migen/genlib/fifo.py b/migen/genlib/fifo.py
index b892e9c4..afb397f8 100644
--- a/migen/genlib/fifo.py
+++ b/migen/genlib/fifo.py
@@ -19,18 +19,18 @@ class _FIFOInterface:
 		self.re = Signal()
 		self.readable = Signal() # not empty
 
-		if isinstance(width_or_layout, (int, tuple)):
-			self.din = Signal(width_or_layout)
-			self.dout = Signal(width_or_layout)
-			self.din_bits = self.din
-			self.dout_bits = self.dout
-			self.width = width_or_layout
-		else:
+		if isinstance(width_or_layout, list):
 			self.din = Record(width_or_layout)
 			self.dout = Record(width_or_layout)
 			self.din_bits = self.din.raw_bits()
 			self.dout_bits = self.dout.raw_bits()
 			self.width = layout_len(width_or_layout)
+		else:
+			self.din = Signal(width_or_layout)
+			self.dout = Signal(width_or_layout)
+			self.din_bits = self.din
+			self.dout_bits = self.dout
+			self.width = width_or_layout
 
 class SyncFIFO(Module, _FIFOInterface):
 	def __init__(self, width_or_layout, depth):