From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 1 Dec 2021 13:41:21 +0000 (+0000)
Subject: FunctionUnitBaseMulti which derives from ReservationStations2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b78413af7966267c44e76c8ac4d9beb90a1fae49;p=soc.git

FunctionUnitBaseMulti which derives from ReservationStations2
*requires* the muxid to be set for each RS.  these can be set
combinatorially no problem, to indicate to ReservationStations2 where
to route the data after it pops out the end of the "real" ALU
without these muxids being set everything is royally screwed
---

diff --git a/src/soc/fu/compunits/compunits.py b/src/soc/fu/compunits/compunits.py
index 8c48a13d..03c28c42 100644
--- a/src/soc/fu/compunits/compunits.py
+++ b/src/soc/fu/compunits/compunits.py
@@ -169,8 +169,17 @@ class FunctionUnitBaseMulti(ReservationStations2):
             palu = self.pseudoalus[idx]
             cu = MultiCompUnit(regspec, palu, opsubset, name=alu_name)
             cu.fnunit = self.fnunit
+            cu.fu_muxidx = idx
             self.cu.append(cu)
 
+    def elaborate(self, platform):
+        m = super().elaborate(platform)
+        # set the muxids so that ReservationStations2 can direct data
+        # without this the incoming data gets routed to the wrong place!
+        # NOTE: for Mask Cancellation this has to be done slightly differently
+        for i, p in enumerate(self.p):
+            m.d.comb += p.i_data.muxid.eq(i)
+        return m
 
 ######################################################################
 ###### actual Function Units: these are "single" stage pipelines #####
diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py
index ee8581e9..83f741e9 100644
--- a/src/soc/simple/test/test_core.py
+++ b/src/soc/simple/test/test_core.py
@@ -213,10 +213,10 @@ class TestRunner(FHDLTestCase):
         comb = m.d.comb
         instruction = Signal(32)
 
-        units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1,
+        units = {'alu': 3, 'cr': 1, 'branch': 1, 'trap': 1,
                  'spr': 1,
                  'logical': 1,
-                 'mul': 1,
+                 'mul': 3,
                  'div': 1, 'shiftrot': 1}
 
         pspec = TestMemPspec(ldst_ifacetype='testpi',