From: lkcl <lkcl@web>
Date: Thu, 25 Mar 2021 14:43:46 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~1153
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b793981873154436b316d56a861b2893d8b3c2a8;p=libreriscv.git

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+# Draft letter
+
+* letter to OpenPOWER Foundation Board of Directors
+* purpose: dialog on how LibreSOC and RED Semiconductor propose extensions
+
+edit history:
+
+* 25mar2021 first revision
+
+# Contents
+
+Dear OPF Board,
+
+As you know the LibreSOC team have been working for over 3 years on a massive conceptual upgrade to the OpenPOWER ISA, based on Cray-Style Vectors, which will modernise it for today's 3D and VPU workloads, with an incidental side-effect of upgrading it for future supercomputing needs.  RISC-V has RVV, ARM has SVE2, x86 has AVX512, whilst OpenPOWER has an out-of-date SIMD ISA. It goes without saying that over the decades, SIMD has been demonstrated to be harmful.
+https://www.sigarch.org/simd-instructions-considered-harmful/