From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 6 Apr 2020 21:08:35 +0000 (+0100)
Subject: add extra info on SPRs
X-Git-Tag: div_pipeline~1439^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b7a04110433fed0b3e3e3044307851f1653d768c;p=soc.git

add extra info on SPRs
---

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index d9986967..1763bcef 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -135,11 +135,13 @@ class ISACaller:
         # TODO, needed here:
         # 4.4.4 III p971 SPR (same as GPR except for SPRs - best done as a dict
         # FPR (same as GPR except for FP nums)
-        # p124 FPSCR
+        # 4.2.2 p124 FPSCR
         # 2.3.1 CR (and sub-fields CR0..CR6)
-        # 2.3.2 LR
-        # 2.3.3 CTR
-        # 2.3.4 TAR
+        # 2.3.2 LR   (SPR #8)
+        # 2.3.3 CTR  (SPR #9)
+        # 2.3.4 TAR  (SPR #815)
+        # 3.2.2 p45 XER  (SPR #0)
+        # 3.2.3 p46 p232 VRSAVE (SPR #256)
 
         self.namespace = {'GPR': self.gpr,
                           'MEM': self.mem,