From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Sun, 10 Jun 2012 15:05:10 +0000 (+0200)
Subject: wishbone: base TargetModel class
X-Git-Tag: 24jan2021_ls180~2099^2~926
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b7a84b37501ac3426af8fb843e278ccf73faa11b;p=litex.git

wishbone: base TargetModel class
---

diff --git a/examples/dataflow_dma.py b/examples/dataflow_dma.py
index a6ccd9a3..9b2491ec 100644
--- a/examples/dataflow_dma.py
+++ b/examples/dataflow_dma.py
@@ -9,16 +9,13 @@ from migen.bus import wishbone
 from migen.sim.generic import Simulator
 from migen.sim.icarus import Runner
 
-class MyModel:
+class MyModel(wishbone.TargetModel):
 	def __init__(self):
 		self.prng = Random(763627)
 	
 	def read(self, address):
 		return address + 4
 	
-	def write(self, address, data, sel):
-		pass
-	
 	def can_ack(self, bus):
 		return self.prng.randrange(0, 2)
 
diff --git a/examples/wb_initiator.py b/examples/wb_initiator.py
index 607de696..0832d4bb 100644
--- a/examples/wb_initiator.py
+++ b/examples/wb_initiator.py
@@ -33,16 +33,13 @@ def my_generator():
 			yield None
 
 # Our bus slave.
-class MyModel:
+class MyModel(wishbone.TargetModel):
 	def __init__(self):
 		self.prng = Random(763627)
 	
 	def read(self, address):
 		return address + 4
 	
-	def write(self, address, data, sel):
-		pass
-	
 	def can_ack(self, bus):
 		return self.prng.randrange(0, 2)
 
diff --git a/migen/bus/wishbone.py b/migen/bus/wishbone.py
index d7a400ae..ae58127e 100644
--- a/migen/bus/wishbone.py
+++ b/migen/bus/wishbone.py
@@ -188,6 +188,16 @@ class Initiator:
 	def get_fragment(self):
 		return Fragment(sim=[self.do_simulation])
 
+class TargetModel:
+	def read(self, address):
+		return 0
+	
+	def write(self, address, data, sel):
+		pass
+	
+	def can_ack(self, bus):
+		return True
+
 class Target:
 	def __init__(self, model):
 		self.bus = Interface()
@@ -196,11 +206,7 @@ class Target:
 	def do_simulation(self, s):
 		bus = Proxy(s, self.bus)
 		if not bus.ack:
-			if hasattr(self.model, "can_ack"):
-				can_ack = self.model.can_ack(bus)
-			else:
-				can_ack = True
-			if can_ack and bus.cyc and bus.stb:
+			if self.model.can_ack(bus) and bus.cyc and bus.stb:
 				if bus.we:
 					self.model.write(bus.adr, bus.dat_w, bus.sel)
 				else: