From: Tobias Platen <tplaten@posteo.de>
Date: Sun, 21 Jul 2019 16:09:19 +0000 (+0200)
Subject: TLB testbench WIP
X-Git-Tag: div_pipeline~1834
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b7aad51f4f5a13a86f347d33abdac841d74a70bd;p=soc.git

TLB testbench WIP
---

diff --git a/src/TLB/TLB.py b/src/TLB/TLB.py
index 3538bdc1..f2b7a925 100644
--- a/src/TLB/TLB.py
+++ b/src/TLB/TLB.py
@@ -5,13 +5,13 @@
     * Tag (N - 79) / ASID (78 - 64) / PTE (63 - 0)
 """
 
-from nmigen import Memory, Module, Signal, Cat
+from nmigen import Memory, Module, Signal, Cat, Elaboratable
 from nmigen.cli import main
 
-from PermissionValidator import PermissionValidator
-from Cam import Cam
+from .PermissionValidator import PermissionValidator
+from .Cam import Cam
 
-class TLB():
+class TLB(Elaboratable):
     def __init__(self, asid_size, vma_size, pte_size, L1_size):
         """ Arguments
             * asid_size: Address Space IDentifier (ASID) typically 15 bits
diff --git a/src/TLB/test/test_tlb.py b/src/TLB/test/test_tlb.py
new file mode 100644
index 00000000..8e26130a
--- /dev/null
+++ b/src/TLB/test/test_tlb.py
@@ -0,0 +1,21 @@
+import tracemalloc
+
+tracemalloc.start()
+
+from nmigen.compat.sim import run_simulation
+
+from TLB.TLB import TLB
+
+from TestUtil.test_helper import assert_op
+
+def tbench(dut):
+    pass
+
+def test_tlb():
+    #FIXME UnusedElaboratable when the following line is uncommented
+    #dut = TLB(15,36,64,8)
+    #run_simulation(dut, tbench(dut), vcd_name="Waveforms/test_tlb.vcd")
+    print("TLB Unit Test TODO")
+
+if __name__ == "__main__":
+    test_tlb()