From: colepoirier <colepoirier@gmail.com>
Date: Fri, 5 Jun 2020 14:12:26 +0000 (-0700)
Subject: Made small changes to fu/trap/main_stage to bring nmigen into line with
X-Git-Tag: div_pipeline~559
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b7b67db86e3199e6f48ce1c0ea798cf8b4dd09f3;p=soc.git

Made small changes to fu/trap/main_stage to bring nmigen into line with
microwatt VHDL
---

diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py
index 964cd6b7..4efb032e 100644
--- a/src/soc/fu/trap/main_stage.py
+++ b/src/soc/fu/trap/main_stage.py
@@ -175,16 +175,16 @@ class TrapMainStage(PipeModBase):
                 """
                 L = self.fields.FormX.L[0:-1]
                 with m.If(L):
-                    comb += msr_o[MSR_EE].eq(msr_i[MSR_EE])
-                    comb += msr_o[MSR_RI].eq(msr_i[MSR_RI])
+                    comb += msr_o.data[MSR_EE].eq(a_i[MSR_EE])
+                    comb += msr_o.data[MSR_RI].eq(a_i[MSR_RI])
 
                 with m.Else():
                     for stt, end in [(1,12), (13, 60), (61, 64)]:
                         comb += msr_o.data[stt:end].eq(a_i[stt:end])
-                    with m.If(a[MSR_PR]):
-                            msr_o[MSR_EE].eq(1)
-                            msr_o[MSR_IR].eq(1)
-                            msr_o[MSR_DR].eq(1)
+                    with m.If(b_in[MSR_PR]):
+                            msr_o.data[MSR_EE].eq(1)
+                            msr_o.data[MSR_IR].eq(1)
+                            msr_o.data[MSR_DR].eq(1)
                 comb += msr_o.ok.eq(1)
 
             # move from SPR