From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 27 Jun 2019 02:58:09 +0000 (-0700)
Subject: Add "WE" to dist RAM's abc_scc_break
X-Git-Tag: working-ls180~1237^2~26
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b7bef15b16abf1674d9c2efc58536db3abaf0e3d;p=yosys.git

Add "WE" to dist RAM's abc_scc_break
---

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 04381e3b9..4ecf8277b 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -281,7 +281,7 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
   always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
 endmodule
 
-(* abc_box_id = 4, abc_scc_break="D" *)
+(* abc_box_id = 4, abc_scc_break="D,WE" *)
 module RAM32X1D (
   output DPO, SPO,
   input  D, WCLK, WE,
@@ -299,7 +299,7 @@ module RAM32X1D (
   always @(posedge clk) if (WE) mem[a] <= D;
 endmodule
 
-(* abc_box_id = 5, abc_scc_break="D" *)
+(* abc_box_id = 5, abc_scc_break="D,WE" *)
 module RAM64X1D (
   output DPO, SPO,
   input  D, WCLK, WE,
@@ -317,7 +317,7 @@ module RAM64X1D (
   always @(posedge clk) if (WE) mem[a] <= D;
 endmodule
 
-(* abc_box_id = 6, abc_scc_break="D" *)
+(* abc_box_id = 6, abc_scc_break="D,WE" *)
 module RAM128X1D (
   output       DPO, SPO,
   input        D, WCLK, WE,