From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 10 Jun 2020 13:25:27 +0000 (+0100)
Subject: TODO on RA immediate-zero mode
X-Git-Tag: div_pipeline~424
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b7c4b06329859cdf237a20b9b52bc5a3fa42d4d7;p=soc.git

TODO on RA immediate-zero mode
---

diff --git a/src/soc/fu/test/common.py b/src/soc/fu/test/common.py
index 607b7074..9a97652e 100644
--- a/src/soc/fu/test/common.py
+++ b/src/soc/fu/test/common.py
@@ -23,6 +23,7 @@ class TestCase:
 class ALUHelpers:
 
     def get_sim_int_ra(res, sim, dec2):
+        # TODO: immediate RA zero
         reg1_ok = yield dec2.e.read_reg1.ok
         if reg1_ok:
             data1 = yield dec2.e.read_reg1.data
@@ -35,6 +36,7 @@ class ALUHelpers:
             res['rb'] = sim.gpr(data).value
 
     def set_int_ra(alu, dec2, inp):
+        # TODO: immediate RA zero.
         if 'ra' in inp:
             yield alu.p.data_i.ra.eq(inp['ra'])
         else: