From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 3 Jun 2018 05:55:31 +0000 (+0100)
Subject: add images
X-Git-Tag: convert-csv-opcode-to-binary~5315
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b7fb09a37997c358d99e151652720059cbeb59a3;p=libreriscv.git

add images
---

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index d6269b489..e83cd4c6b 100644
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -197,15 +197,17 @@
 \frame{\frametitle{How are SIMD Instructions Vectorised?}
 
  \begin{itemize}
-   \item SIMD ALU(s) primarily unchanged\vspace{10pt}
-   \item Predication is added to each SIMD element (NO ZEROING!)\vspace{10pt}
-   \item End of Vector enables predication (NO ZEROING!)\vspace{10pt}
+   \item SIMD ALU(s) primarily unchanged\vspace{6pt}
+   \item Predication is added to each SIMD element\vspace{6pt}
+   \item Predication bits sent in groups to the ALU\vspace{6pt}
+   \item End of Vector enables (additional) predication\vspace{10pt}
   \end{itemize}
-  Considerations:\vspace{10pt}
+  Considerations:\vspace{4pt}
    \begin{itemize}
-   \item Many SIMD ALUs possible (parallel execution)\vspace{10pt}
-   \item Very long SIMD ALUs could waste die area (short vectors)\vspace{10pt}
-   \item Implementor free to choose (API remains the same)\vspace{10pt}
+   \item Many SIMD ALUs possible (parallel execution)
+   \item Implementor free to choose (API remains the same)
+   \item Unused ALU units wasted, but s/w DRASTICALLY simpler 
+   \item Very long SIMD ALUs could waste significant die area
   \end{itemize}
 }
 % With multiple SIMD ALUs at for example 32-bit wide they can be used