From: Eric Anholt <eric@anholt.net>
Date: Thu, 6 Dec 2012 19:35:28 +0000 (-0800)
Subject: i965: Add the new flag_reg_nr instruction field from IVB.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b7fd4b3f9419353732a061920aefdc7bcec4728d;p=mesa.git

i965: Add the new flag_reg_nr instruction field from IVB.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
---

diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c b/src/mesa/drivers/dri/i965/brw_disasm.c
index 1f3aecad8bc..b18676df7a7 100644
--- a/src/mesa/drivers/dri/i965/brw_disasm.c
+++ b/src/mesa/drivers/dri/i965/brw_disasm.c
@@ -1048,7 +1048,7 @@ int brw_disasm (FILE *file, struct brw_instruction *inst, int gen)
     if (inst->header.predicate_control) {
 	string (file, "(");
 	err |= control (file, "predicate inverse", pred_inv, inst->header.predicate_inverse, NULL);
-	string (file, "f0");
+	format (file, "f%d", gen >= 7 ? inst->bits2.da1.flag_reg_nr : 0);
 	if (inst->bits2.da1.flag_subreg_nr)
 	    format (file, ".%d", inst->bits2.da1.flag_subreg_nr);
 	if (inst->header.access_mode == BRW_ALIGN_1)
diff --git a/src/mesa/drivers/dri/i965/brw_structs.h b/src/mesa/drivers/dri/i965/brw_structs.h
index ac817b9ee48..a8196b6ee4d 100644
--- a/src/mesa/drivers/dri/i965/brw_structs.h
+++ b/src/mesa/drivers/dri/i965/brw_structs.h
@@ -1065,7 +1065,8 @@ struct brw_instruction
 	 GLuint src0_width:3;
 	 GLuint src0_vert_stride:4;
 	 GLuint flag_subreg_nr:1;
-	 GLuint pad:6;
+	 GLuint flag_reg_nr:1;
+	 GLuint pad:5;
       } da1;
 
       struct
@@ -1079,7 +1080,8 @@ struct brw_instruction
 	 GLuint src0_width:3;
 	 GLuint src0_vert_stride:4;
 	 GLuint flag_subreg_nr:1;
-	 GLuint pad:6;	
+	 GLuint flag_reg_nr:1;
+	 GLuint pad:5;
       } ia1;
 
       struct
@@ -1096,7 +1098,8 @@ struct brw_instruction
 	 GLuint pad0:1;
 	 GLuint src0_vert_stride:4;
 	 GLuint flag_subreg_nr:1;
-	 GLuint pad1:6;
+	 GLuint flag_reg_nr:1;
+	 GLuint pad1:5;
       } da16;
 
       struct
@@ -1113,7 +1116,8 @@ struct brw_instruction
 	 GLuint pad0:1;
 	 GLuint src0_vert_stride:4;
 	 GLuint flag_subreg_nr:1;
-	 GLuint pad1:6;
+	 GLuint flag_reg_nr:1;
+	 GLuint pad1:5;
       } ia16;
 
       /* Extended Message Descriptor for Ironlake (Gen5) SEND instruction.