From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 21 Jun 2019 02:40:17 +0000 (-0700)
Subject: write_xaiger to flatten 1'bx/1'bz to 1'b0 again
X-Git-Tag: working-ls180~1208^2~126
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b810bf26ab9e40e8d7e5a5001ac3a1708309a30b;p=yosys.git

write_xaiger to flatten 1'bx/1'bz to 1'b0 again
---

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 55a95d835..82f0f24b2 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -104,8 +104,10 @@ struct XAigerWriter
 				aig_map[bit] = bit2aig(alias_map.at(bit));
 			}
 
-			if (bit == State::Sx || bit == State::Sz)
-				log_error("Design contains 'x' or 'z' bits. Use 'setundef' to replace those constants.\n");
+			if (bit == State::Sx || bit == State::Sz) {
+				log_debug("Bit '%s' contains 'x' or 'z' bits. Treating as 1'b0.\n", log_signal(bit));
+				aig_map[bit] = 0;
+			}
 		}
 
 		log_assert(aig_map.at(bit) >= 0);