From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 3 Jun 2020 11:43:25 +0000 (+0100)
Subject: correct overflow-enable flags for rdmask specs in ALU
X-Git-Tag: div_pipeline~637^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b8166f4bf226a88a7c057bb7b10fc0bc2b009bed;p=soc.git

correct overflow-enable flags for rdmask specs in ALU
---

diff --git a/src/soc/decoder/power_regspec_map.py b/src/soc/decoder/power_regspec_map.py
index 662159a3..29f8e4b9 100644
--- a/src/soc/decoder/power_regspec_map.py
+++ b/src/soc/decoder/power_regspec_map.py
@@ -70,11 +70,11 @@ def regspec_decode(e, regfile, name):
         CA = 1<<XERRegs.CA
         OV = 1<<XERRegs.OV
         if name == 'xer_so':
-            #return e.oe.oe & e.oe.oe_ok, SO, SO
+            return e.oe.oe[0] & e.oe.oe_ok, SO, SO
             return Const(1), SO, SO # TODO
         if name == 'xer_ov':
+            return e.oe.oe[0] & e.oe.oe_ok, OV, OV
             return Const(1), OV, OV # TODO
-            return e.oe.oe & e.oe.oe_ok, OV, OV
         if name == 'xer_ca':
             return Const(1), CA, CA # TODO
             #return e.input_carry, CA, CA
diff --git a/src/soc/fu/compunits/test/test_alu_compunit.py b/src/soc/fu/compunits/test/test_alu_compunit.py
index 87ba1bc7..ff2adcc5 100644
--- a/src/soc/fu/compunits/test/test_alu_compunit.py
+++ b/src/soc/fu/compunits/test/test_alu_compunit.py
@@ -39,8 +39,8 @@ class ALUTestRunner(TestRunner):
             res['xer_ca'] = carry | (carry32<<1)
 
         # XER.so
-        oe = yield dec2.e.oe.data & dec2.e.oe.ok
-        if True: #oe:
+        oe = yield dec2.e.oe.data[0] & dec2.e.oe.ok
+        if oe:
             so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
             res['xer_so'] = so