From: lkcl <lkcl@web>
Date: Thu, 21 Apr 2022 08:19:03 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2663
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b8191012cdd9cc01c46ade4becc1d0e97958c7c0;p=libreriscv.git

---

diff --git a/openpower/sv/biginteger.mdwn b/openpower/sv/biginteger.mdwn
index bfd566cfd..52735f50c 100644
--- a/openpower/sv/biginteger.mdwn
+++ b/openpower/sv/biginteger.mdwn
@@ -20,6 +20,10 @@ Dynamic SIMD ALUs for maximum performance and effectiveness.
 
 # Analysis
 
+Covered in [[analysis]] the summary is that standard `adde` is sufficient
+for SVP64 Vectorisation, but that big-integer multiply and divide
+require two extra 3-in 2-out instructions, similar to Intel's `mulx`.
+
 This section covers an analysis of big integer operations.  Use of
 smaller sub-operations is a given: worst-case, addition is O(N)
 whilst multiply and divide are O(N^2).