From: Gabor Dozsa <gabor.dozsa@arm.com>
Date: Thu, 15 Feb 2018 11:46:19 +0000 (+0000)
Subject: cpu-o3: Reset fault status for mem access in pushRequest
X-Git-Tag: v19.0.0.0~739
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b81a66d7751124cb78d521bc259742c39a28b902;p=gem5.git

cpu-o3: Reset fault status for mem access in pushRequest

Reset the fault status always before translation is initiated in
pushRequest() in the LSQ. This avoids the problem when a strictly
ordered load needs to be re-executed multiple times. If the
translation is delayed at one of those attempts then the
internal panicFault (from the previous execution attempt) can get
fired at commit.

Change-Id: I0c22b2f7afd6e2cb00bc359a4a01042efd2d01d2
Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19388
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index 70621a523..d4e0a289e 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -724,6 +724,10 @@ LSQ<Impl>::pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
         inst->setRequest();
         req->taskId(cpu->taskId());
 
+        // There might be fault from a previous execution attempt if this is
+        // a strictly ordered load
+        inst->getFault() = NoFault;
+
         req->initiateTranslation();
     }