From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 10 Jul 2021 11:37:20 +0000 (+0100)
Subject: add sv.ffadds unit test, inversion of subtract needed in svfparith pseudocode
X-Git-Tag: xlen-bcd~307
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b822641c648fa3016a1abc960d6e0d8d3aaad1ec;p=openpower-isa.git

add sv.ffadds unit test, inversion of subtract needed in svfparith pseudocode
---

diff --git a/openpower/isa/svfparith.mdwn b/openpower/isa/svfparith.mdwn
index 1bcc1ac7..021a7c3d 100644
--- a/openpower/isa/svfparith.mdwn
+++ b/openpower/isa/svfparith.mdwn
@@ -15,7 +15,7 @@ A-Form
 Pseudo-code:
 
     FRT <- FPADD32(FRA, FRB)
-    FRS <- FPSUB32(FRA, FRB)
+    FRS <- FPSUB32(FRB, FRA)
 
 Special Registers Altered:
 
@@ -34,7 +34,7 @@ A-Form
 Pseudo-code:
 
     FRT <- FPADD64(FRA, FRB)
-    FRS <- FPSUB64(FRA, FRB)
+    FRS <- FPSUB64(FRB, FRA)
 
 Special Registers Altered:
 
@@ -52,7 +52,7 @@ A-Form
 
 Pseudo-code:
 
-    FRT <- FPSUB32(FRA, FRB)
+    FRT <- FPSUB32(FRB, FRA)
     FRS <- FPADD32(FRA, FRB)
 
 Special Registers Altered:
@@ -71,7 +71,7 @@ A-Form
 
 Pseudo-code:
 
-    FRT <- FPSUB64(FRA, FRB)
+    FRT <- FPSUB64(FRB, FRA)
     FRS <- FPADD64(FRA, FRB)
 
 Special Registers Altered:
diff --git a/src/openpower/decoder/isa/test_caller_svp64_fft.py b/src/openpower/decoder/isa/test_caller_svp64_fft.py
index 5b93281a..2204fea2 100644
--- a/src/openpower/decoder/isa/test_caller_svp64_fft.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_fft.py
@@ -331,6 +331,57 @@ class FFTTestCase(FHDLTestCase):
                 self.assertEqual(sim.fpr(i+2), t)
                 self.assertEqual(sim.fpr(i+6), u)
 
+    def test_sv_ffadds_fft(self):
+        """>>> lst = ["sv.ffadds 2.v, 2.v, 2.v"
+                        ]
+            four in-place vector adds, four in-place vector subs
+
+            SVP64 "FFT" mode will *automatically* offset FRB and an implicit
+            FRS to perform the two multiplies.  one add, one subtract.
+
+            sv.ffadds FRT, FRA, FRB  actually does:
+                fadds FRT   , FRA, FRA
+                fsubs FRT+vl, FRA, FRB+vl
+        """
+        lst = SVP64Asm(["sv.ffadds 2.v, 2.v, 2.v"
+                        ])
+        lst = list(lst)
+
+        fprs = [0] * 32
+        av = [7.0, -9.8, 2.0, -32.3] # first half of array 0..3
+        bv = [-2.0, 2.0, -9.8, 32.3] # second half of array 4..7
+        res = []
+        # work out the results with the twin add-sub
+        for i, (a, b) in enumerate(zip(av, bv)):
+            fprs[i+2] = fp64toselectable(a)
+            fprs[i+6] = fp64toselectable(b)
+            t = b + a
+            u = b - a
+            t = DOUBLE2SINGLE(fp64toselectable(t)) # convert to Power single
+            u = DOUBLE2SINGLE(fp64toselectable(u)) # from double
+            res.append((t, u))
+            print ("FFT", i, "in", a, b, "res", t, u)
+
+        # SVSTATE (in this case, VL=2)
+        svstate = SVP64State()
+        svstate.vl[0:7] = 4 # VL
+        svstate.maxvl[0:7] = 4 # MAXVL
+        print ("SVSTATE", bin(svstate.spr.asint()))
+
+        with Program(lst, bigendian=False) as program:
+            sim = self.run_tst_program(program, svstate=svstate,
+                                       initial_fprs=fprs)
+            # confirm that the results are as expected
+            for i, (t, u) in enumerate(res):
+                a = float(sim.fpr(i+2))
+                b = float(sim.fpr(i+6))
+                t = float(t)
+                u = float(u)
+                print ("FFT", i, "in", a, b, "res", t, u)
+            for i, (t, u) in enumerate(res):
+                self.assertEqual(sim.fpr(i+2), t)
+                self.assertEqual(sim.fpr(i+6), u)
+
     def tst_sv_remap_fpmadds_fft_svstep_complex(self):
         """
             runs a full in-place O(N log2 N) butterfly schedule for
diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index f3b13879..05f97632 100644
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -983,7 +983,7 @@ if __name__ == '__main__':
     lst = [
              'sv.fmadds 0.v, 8.v, 16.v, 4.v',
              'svremap 8, 1, 1, 1',
-             'sv.fadds 0.v, 8.v, 4.v',
+             'sv.ffadds 0.v, 8.v, 4.v',
             ]
     isa = SVP64Asm(lst, macros=macros)
     print ("list", list(isa))