From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 23 Sep 2019 20:58:10 +0000 (-0700)
Subject: Comment to explain separating CREG packing
X-Git-Tag: working-ls180~1039^2~40
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b824a56cde5aa692da2dc6b6a0d161a98daac6ef;p=yosys.git

Comment to explain separating CREG packing
---

diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
index 86472feb5..a145ab184 100644
--- a/passes/pmgen/xilinx_dsp.cc
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -606,6 +606,14 @@ struct XilinxDspPass : public Pass {
                 xilinx_dsp_pm pm(module, module->selected_cells());
                 pm.run_xilinx_dsp_pack(xilinx_dsp_pack);
             }
+            // Separating out CREG packing is necessary since there
+            //   is no guarantee that the cell ordering corresponds
+            //   to the "expected" case (i.e. the order in which
+            //   they appear in the source) thus the possiblity
+            //   existed that a register got packed as CREG into a
+            //   downstream DSP that should have otherwise been a
+            //   PREG of an upstream DSP that had not been pattern
+            //   matched yet
             {
                 xilinx_dsp_CREG_pm pm(module, module->selected_cells());
                 pm.run_xilinx_dsp_packC(xilinx_dsp_packC);