From: Stefan Biereigel <stefan@biereigel.de>
Date: Mon, 3 Feb 2020 20:29:40 +0000 (+0100)
Subject: correct wire declaration grammar for #1614
X-Git-Tag: working-ls180~801^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b844b078db0c8b61758c562fbb8324bd5013bfa1;p=yosys.git

correct wire declaration grammar for #1614
---

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index a30935e0a..96f2faaa1 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -476,7 +476,7 @@ wire_type:
 		astbuf3 = new AstNode(AST_WIRE);
 		current_wire_rand = false;
 		current_wire_const = false;
-	} wire_type_token_list delay {
+	} wire_type_token_list {
 		$$ = astbuf3;
 	};
 
@@ -1240,7 +1240,7 @@ wire_decl:
 		}
 		if (astbuf2 && astbuf2->children.size() != 2)
 			frontend_verilog_yyerror("wire/reg/logic packed dimension must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]");
-	} wire_name_list {
+	} delay wire_name_list {
 		delete astbuf1;
 		if (astbuf2 != NULL)
 			delete astbuf2;