From: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Date: Thu, 11 Jun 2020 13:39:46 +0000 (+0200)
Subject: radv: make sure to set CB_SHADER_MASK correctly for internal CB operations
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b848d88059b17b221e5fa12afe9876862f18623b;p=mesa.git

radv: make sure to set CB_SHADER_MASK correctly for internal CB operations

It should be always set to 0xf.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5427>
---

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index f6365292f51..76244ecf503 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -5119,6 +5119,17 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
 			blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
 	}
 
+	if (extra &&
+	    (extra->custom_blend_mode == V_028808_CB_ELIMINATE_FAST_CLEAR ||
+	     extra->custom_blend_mode == V_028808_CB_FMASK_DECOMPRESS ||
+	     extra->custom_blend_mode == V_028808_CB_DCC_DECOMPRESS ||
+	     extra->custom_blend_mode == V_028808_CB_RESOLVE)) {
+		/* According to the CB spec states, CB_SHADER_MASK should be
+		 * set to enable writes to all four channels of MRT0.
+		 */
+		blend.cb_shader_mask = 0xf;
+	}
+
 	for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
 		if (pipeline->shaders[i]) {
 			pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;