From: Luke Kenneth Casson Leighton Date: Thu, 28 Jul 2022 03:54:25 +0000 (+0100) Subject: clarify X-Git-Tag: opf_rfc_ls005_v1~985 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b84b1e82713238d4cbcc554d184df0beaad34045;p=libreriscv.git clarify --- diff --git a/openpower/sv/comparison_table.mdwn b/openpower/sv/comparison_table.mdwn index 0d90d3787..acaedb9c1 100644 --- a/openpower/sv/comparison_table.mdwn +++ b/openpower/sv/comparison_table.mdwn @@ -35,7 +35,7 @@ * (20): Like the original Cray RVV is a truly scalable Vector ISA (Cray setvl instruction). However, like SVE2, the Maximum Vector length is a Silicon-partner choice, which creates similar limitations that SVP64 does not have. The RISC-V Founders strongly discouraged efforts by programmers to find out the Maximum Vector Length, as an effort to steer programmers towards Silicon-independent assembler. This requires all algorithms to contain a loop construct. MAXVL in SVP64 is a Spec-hard-fixed quantity therefore loop constructs are not necessary 100% of the time. -* (21): like SVP64 it is up to the hardware implementor to choose whether to support 128-bit elements. +* (21): like SVP64 it is up to the hardware implementor (Silicon partner) to choose whether to support 128-bit elements. * (22): [NEC SX Aurora](https://ftp.libre-soc.org/NEC_SX_Aurora_TSUBASA_VectorEngine-as-manual-v1.2.pdf) is based on the original Cray Vectors * (23): [Aurora ISA guide](https://sxauroratsubasa.sakura.ne.jp/documents/guide/pdfs/Aurora_ISA_guide.pdf) Appendix-3 11.1 p508 * (24): Like the original Cray Vectors, the ISA Vector Length is independent of the underlying hardware, however Generation 1 has 256 elements per Vector register (3.2.4 p24, Aurora ISA guide)