From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 19 Mar 2022 11:48:37 +0000 (+0000)
Subject: disable hyperram for now (under investigation)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b864f61b488f740c957105ba073fb695f4b74167;p=ls2.git

disable hyperram for now (under investigation)
---

diff --git a/src/ls2.py b/src/ls2.py
index 05966db..4f63cc3 100644
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -467,7 +467,9 @@ class DDR3SoC(SoC, Elaboratable):
 
         # add hyperram module
         if hasattr(self, "hyperram"):
-            m.submodules.hyperram = self.hyperram
+            m.submodules.hyperram = hyperram = self.hyperram
+            # grrr, same problem with hyperram: not WB4-pipe compliant
+            comb += hyperram.bus.stall.eq(hyperram.bus.cyc & ~hyperram.bus.ack)
 
         # add blinky lights so we know FPGA is alive
         if platform is not None:
@@ -623,6 +625,9 @@ if __name__ == "__main__":
     else:
         hyperram_pins = HyperRAMPads()
 
+    # broken at the moment
+    hyperram_pins = None
+
     # set up the SOC
     soc = DDR3SoC(fpga=fpga, dram_cls=dram_cls,
                   # check microwatt_soc.h for these