From: Daniel Benusovich <flyingmonkeys1996@gmail.com>
Date: Mon, 1 Apr 2019 01:23:49 +0000 (-0700)
Subject: Correcting read/write port assignments
X-Git-Tag: div_pipeline~2282
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b866bd132f3ddd99c36d0499dda888c7980f43dc;p=soc.git

Correcting read/write port assignments
---

diff --git a/TLB/src/TLB.py b/TLB/src/TLB.py
index adf6b971..aaa55da2 100644
--- a/TLB/src/TLB.py
+++ b/TLB/src/TLB.py
@@ -55,8 +55,8 @@ class TLB():
             # Add submodules
             # Submodules for L1 Cache
             m.d.submodules.cam_L1 = self.cam_L1
-            m.d.sumbmodules.read_L1 = read_L1 = self.mem_L1.read_port
-            m.d.sumbmodules.read_L1 = write_L1 = self.mem_L1.read_port
+            m.d.sumbmodules.read_L1 = read_L1 = self.mem_L1.read_port()
+            m.d.sumbmodules.read_L1 = write_L1 = self.mem_L1.write_port()
             # Permission Validator Submodule
             m.d.submodules.perm_valididator = self.perm_validator