From: tklam <tklam@easylogic.hk>
Date: Wed, 26 Sep 2018 09:57:39 +0000 (+0800)
Subject: fix bug: pass by reference
X-Git-Tag: yosys-0.9~448^2~4
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b86eb3deef7d80fc5450379c80047636832ef458;p=yosys.git

fix bug: pass by reference
---

diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc
index 8590c820b..e74dab36f 100644
--- a/passes/equiv/equiv_make.cc
+++ b/passes/equiv/equiv_make.cc
@@ -404,7 +404,7 @@ struct EquivMakeWorker
 		}
 	}
 
-	bool check_signal_in_fanout(pool<Cell*> visited_cells, SigBit source_bit, SigBit target_bit)
+	bool check_signal_in_fanout(pool<Cell*> & visited_cells, SigBit source_bit, SigBit target_bit)
 	{
 		if (source_bit == target_bit)
 			return true;